Today, a trend of high-density NMOS NVSRAM memory more than 8 Mb is required. Therefore, besides the fixed six transistors (6T) of each SRAM cell, the number of transistors of each NMOS Flash cell should be minimized as much as possible.
Traditionally, a 12T NVSRAM cell comprises one 6T LV SRAM cell and one 6T HV Flash cell including paired 3T Flash strings. Each SRAM cell has paired storage nodes of Q and QB connected to two inputs of the paired Flash strings. Each 3T Flash string further includes one HV Select transistor located on top and another one on bottom, with one 2-poly HV flash transistor sandwiched in the middle of above two HV Select transistors.
Each paired drain nodes of the paired Flash strings are preferably connected to each paired nodes of Q and QB of each 6T LV SRAM cell directly. Conversely, the paired source nodes of each paired Flash strings are connected to a common VDD power supply to provide the different current flows to charge each paired nodes of Q and QB at two different voltage levels for each SRAM cell's subsequent amplification through two different programmed Vts of each paired Flash transistors during the Recall operation.
Although several NVSRAM approaches were disclosed before, the conventional 12T NVSRAM cell using low-current FN-channel program and FN SBPI method is prevailing in the market place. The flash type can be either made of 1-poly charge-trapping SONOS or MONOS type from Cypress or 2-poly floating-gate NMOS or PMOS type from Aplus Flash Technology, Inc., or a trigate flash technology from Simtek. By 2012, the highest density of a 12T NMOS NVSRAM memory in production is 16 Mb.
One big drawback of this 12T NMOS NVSRAM memory is its large 12T cell size that comprises one 6T LV SRAM cell and one 6T HV Flash cell. And each 6T Flash cell further comprises one pair of 3T FStrings and each FString further comprises one top HV Select transistor, one bottom HV Select transistor, and one flash transistor sandwiched by two Select transistors in the middle.
Due to three transistors of each Flash string have to be made of all HV devices to sustain a HV of 5-7V generated by a SBPI (Self-Boosting Program-Inhibit) scheme during the FN-Channel Program operation of NVSRAM cell, the channel length of these two HV Select transistors are made relatively bigger than the ones of a LV SRAM's two PMOS and our NMOS transistors. As a result, it is desirable to achieve any saving of each HV Select transistor in each Flash string so as to drastically reduce the NVSRAM cell size for cost reduction.